Synchronization and clock/data recovery operations and related phase and timing applications require timing adjustments after a timing or phase error is detected. Digital approaches are now starting to take the place of analog phase locked loop approaches for data recovery. Due to the advent of integrated circuit technology and especially the development of the complimentary metal oxide silicon (CMOS) circuits, inexpensive all digital data recovery circuit are now possible. For example, delay techniques are known which employ a long chain of single stage CMOS inverters wherein the delay of the single inverter gate is the minimum delay step and the total delay is controlled by selecting the length of the chain. As the requirement for increased frequency of data transmission advances, a need arises to meet timing requirements having finer timing resolution than the delay through a single CMOS inverter stage. Currently the achievable smallest inverter stage delay is in the range of a few hundred picoseconds.
It is known that bias control of a gate will vary the propagation time through a single gate. This concept has been previously employed with analog control but requires expensive noise filtering.